As semiconductor devices are highly integrated, the sizes of such devices are also reduced. This size reduced semiconductor has resulted in a reduction in channel length of a semiconductor device. However, the reduction in the channel length may cause undesired electrical characteristics such as a short channel effect. To obviate the short channel effect, vertical reductions such as reduction in the thickness of a gate insulating layer and the depth ofsource/drainjunctions as well as horizontal reductions such as reduction in the length of a gate electrode have to be achieved. According to the vertical and horizontal reductions, a low voltage has to be applied to a semiconductor device and a high dopant concentration in a semiconductor substrate is required. In addition, the doping profile in a channel region has to be effectively controlled.
However, the voltage used to operate electronics has not been lowered yet although the size of semiconductor devices have considerably been reduced. Therefore, for example, in an metal-oxide semiconductor (N-MOS) transistor, the electrons implanted into a source region are rapidly accelerated due to the high potential gradient of a drain region, thereby causing hot carriers. To obviate such generation of hot carriers, a lightly doped drain (LDD) structure has been suggested. In a transistor with LDD regions, low concentration (n-) regions are positioned between a channel region and high concentration (n-) source/drain regions. The low concentration (n-) regions absorb a high drain voltage around the source/drain regions to obviate a sharp potential gradient, thereby suppressing the generation of hot carriers. With the development of high-integration semiconductor device technology, various technologies of fabricating a metal oxide semiconductor field effect transistor (MOSFET) with LDD regions have been developed. Particularly, one of the technologies most widely used is a method of forming LDD regions after spacers are formed on the sidewalls of a gate electrode.
However, with a continual high-integration of semiconductor devices, just the LDD structure alone could not sufficiently control short channel effects; the spacer fabrication cannot be controlled. Therefore, a halo implant process has been suggested to prevent the source/drain depletion regions from being horizontally closer together while the doping concentration of a channel region, which determines the threshold voltage of a transistor, is not influenced.
The halo implant process forms halo structures around the source/drain regions by implanting impurities with the opposite type to that of impurities in the source/drain regions into the substrate around the source/drain regions. In other words, by surrounding diffusion regions, which have a higher imparity concentration than that of peripheral well regions, around the source/drain regions, the halo implant process reduces the length of source/drain depletion regions.
However, in performing a conventional halo implant process to fabricate a MOS transistor, the impurities doped into the source/drain regions, such as baron or phosphorus, may be diffused into a channel region when a thermal treatment process is performed to form source/drain junctions. Such impurities diffused into the channel region deteriorate the electric characteristics of the MOS transistor. In other words, because the threshold voltage of the MOS transistor changes from an original desired value due to the diffused impurities, it is difficult to distinguish sharply between turn-off and turn-on operations of the MOS transistor. Therefore, the malfunction of the MOS transistor and an increase in a leakage current are caused.
In addition to the short channel effect, the high-integration of semiconductor devices may induce the occurrence of a leakage current and an increase in contact resistance. Moreover, parasitic resistances, which are formed in a semiconductor substrate and a gate electrode, may deteriorate the electric characteristics of a device.